After finally getting my FPGA CoCo up and running, I think it’s time to get back to work on Slim’s SWTPC, so I’m using the winter 2011 Retrochallenge as a motivator to put together a memory board that can be used to boot OS-9 Level I. None of the memory boards that came to me with the computer have enough capacity, though I could probably put 56K together with several. But they also appear to be unreliable. So I intend to make a 64K memory board using 2 32K x 8-bit static RAM chips pulled from the level 2 cache of Pentium or ’486 motherboards.
I would eventually like to put together at least 256K of static RAM on a board and make use of the SWTPC’s DAT to run OS-9 Level II. But I want to start with a simpler rendition of it, and 64K would be adequate to boot OS-9 LI. For me, that should feel like a minor accomplishment, and running OS-9 LI ought to motivate me to make LII work. That may require a little back-porting from the CoCo 3, because I don’t know of any Level II boot disk images for the SWTPC. (If anyone has any, I would be interested.) The CoCo 3′s DAT uses 8K blocks, while the SWTPC uses 4K blocks. This will require a little rework — probably to OS9P2. Otherwise, I think the Level I device drivers for the SWTPC hardware should work OK in Level II. But all that plus a more complicated memory board is probably too much for a January project.
This afternoon I sat down to figure out a few of the details of the board I’ll have to make. I found the schematic for a 32K static RAM board on Mike Holley’s web site, which shows me that I’m on the right track. But I want my board to use 2 32K chips, and I need to disable the the chip select on the SRAMs when the upper 8K of memory is being accessed, because that’s where the I/O devices and ROM are mapped in the SWTPC. Actually, if I change the addresses in the OS-9 device descriptors I think I can move them all into the uppermost 4K of memory, along with the 2K monitor ROM, leaving an additional 4K (very precious in an OS-9 Level I system) available for programs.
Mike Holley’s SRAM board uses a 74ls139 to provide Chip Select and whatnot, but since his memory board is far from interfering with I/O and ROM, it can get by with a very simple decode circuit. To do what I want to do, I think I’m going to have to use a GAL16V8. I have the hardware to burn the fusemap on a GAL, and I should have a few of the chips around. Also, since they’re electrically erasable I can change it if I decide to move the I/O addresses up and free up an additional 4K.
Here’s my first stab at the logic equations for the decoder GAL:
GAL16V8
# Decode circuit for 32K SRAM board for SWTPC
# Ver. 1
#
# Syn = 0
# AC0 = 0
# AC1(n) = 0,0,0,0,0,0,0,0
Clk A15 A14 A13 /VMA /E RW NC1 NC2 GND
/R0CS /R1CS /WR /RD /BUFOE NC3 NC4 NC5 NC6 Vcc
R0CS = /A15 * /A14 * /A13 * VMA
R1CS = A15 * /A14 * /A13 * VMA
WR = /RW * /E * /A14 * /A13 * VMA
RD = RW * /E * /A14 * /A13 * VMA
BUFOE = /A14 * /A13 * VMA








